2025 Theses Doctoral

Scalable Chip Design for Tile-Based Heterogeneous Architectures

Cassel dos Santos, Maico dos

System-on-Chip (SoC) design never has posed so many challenges as today. With the slowdown of Moore’s Law and the end of Dennard scaling, performance gains shifted from device scaling to architectural innovations. After mid-2000s, multi-core processors supplanted single-core processors to improve performance through parallelism. Not long after, the diminishing returns in performance by adding cores marked the rise of heterogeneous SoCs. By combining general purpose cores and specialized hardware accelerators, these architectures deliver superior performance and energy efficiency compared to homogeneous SoCs, at the cost of more design complexity.

The combined escalation of SoC architectural complexity, electronic design automation (EDA) tool sophistication to handle large high-density designs, and advanced semiconductor technology process have driven steep increases in non-recurrent engineering (NRE) costs. State-of-the-art SoCs now demand investments of hundreds of millions of dollars. Compounding this issue, industry projections indicate a significant shortage of skilled semiconductor engineers in the coming years. In response, the open-source hardware (OSH) community has sought to mitigate design complexity by promoting reuse through shared component libraries, design methodologies, and software-hardware platforms.

Despite these efforts, most of the heterogeneous SoCs based on OSH that have been presented in the literature are limited to a few accelerators and general-purpose processors. This limitation stems from the complexity of designing and integrating such architectures, as well as the high degree of customization required across architecture, process technology, and EDA tools. To foster the development of complex SoC, design methodologies must support scalability, flexibility across diverse applications, and robustness in achieving correct layouts - all with minimal NRE cost. My thesis is that a scalable, flexible, and robust chip design methodology for domain-specific SoC has its foundation on the regularity of heterogeneous tile-based architectures, which enable computer-aided design tools to handle efficiently the complexity of chip design.

Throughout this dissertation, I demonstrate how tile-based architectures, when combined with a tailored design methodology, facilitate the partitioning and integration of hardware components, simplify the design flow, promote automation, and significantly reduce NRE costs. The methodology builds on ESP, an open-source platform for tile-based heterogeneous SoC design, by extending its capabilities to support full chip implementation through the introduction of solutions that address all aspects of the flow, including the design hierarchy, clock- and power- domain strategies, physical implementation of individual tiles, and top-level integration.

The potential of the methodology is demonstrated through the successful tape-out of two chips: EPOCHS-0 and EPOCHS-1. Both were fabricated in a 12 nm technology, completed in under four months, and designed by a team of fewer than ten people, including researchers, PhD students, and postdoctoral fellows from multiple institutions. EPOCHS-0 (4×4 tiles) integrates seven accelerators, four RISC-V CVA6 cores, and memory tiles with off-chip interfaces. EPOCHS-1 scales to 6×6 tiles with 23 accelerators of 14 distinct types, Linux symmetric multiprocessing (SMP) support, and distributed power management - arguably the most complex SoC to date designed in an academic environment. This scalability was made possible through OSH and the reuse of community-developed accelerators. Lessons learned from these chips guided further improvements to the methodology, including a more reliable design hierarchy, automated top-level floorplanning, and a customized top-level clock tree tailored for tile-based architectures, which delivers superior scalability compared to default EDA tool configurations.

The contributions of this dissertation will remain with the System-Level Design Group at Columbia University, to realize further improvements and future ESP-based chip designs.