2019 Theses Doctoral
Fully Integrated Digital Low-Drop-Out Regulator Design based on Event-Driven PI Control
A system-on-chip (SoC) with near-threshold supply voltage (NTV) operation has received a significant amount of attention. Its high energy-efficiency supports a number of low-power emerging applications such as wireless sensor networks and Internet-of-Thing edge devices. Integrating various digital, analog, mixed-signal, and power sub-systems, such SoC designs need to employ tens of voltage domains to push the envelope of energy-efficiency, performance, and robustness. A low-drop-out (LDO) regulator is a key building block for creating voltage domains on a chip thanks to its high power density.
In particular, its digital implementation, i.e., digital LDO, recently has emerged as a popular topology since it can support a wide range of input voltage from super-threshold to near-threshold voltage regimes, while conventional analog LDOs become less effective. One of the critical overheads in existing digital LDO designs is a requirement of off-chip output capacitor for stabilizing the output voltage, due to inadequate latency in active control paths. It is possible to employ higher clock frequency in a digital LDO; however such solutions inevitably increase power dissipation. This off-chip capacitor overhead can significantly increase chip pin count and printed circuit board (PCB) space, thus limiting the number of power domains that an SoC can have.
This thesis presents my research on fully-integrated digital LDO designs based on event-driven control architecture. My research focuses on scaling down the output capacitor size to the integrable level and improving transient performance such as maximum voltage change and settling time. To shrink the output capacitor size, we introduced the event-driven control and the binary digital PI controller in our first event-driven LDO design. Thanks to the event-driven control, we achieved control loop latency reduction without compromising power consumption, leading to output capacitor size reduction. The first design shows 2.7x improvement over the previous digital LDO designs in Figure-of-Merit with a 400pF of output capacitor. To further reduce output capacitor size and support larger load current, we implemented the second event-driven digital LDO designs with fine-grained parallelism. The parallel structure of its PI controller reduces the latency of the proportional part, which mainly regulates output voltage, so it achieves better transient performance with reduced size of capacitor. Also, the parallel-shift-register-based integration part lowers computation and area overheads. The second design outperforms the state of the arts by over 17x in Figure-of-Merits with only a 100pF of output capacitor. In the last design, we introduced initialization and self-triggering control. The initialization estimates load current change in the beginning of regulation process and sets the controller output close to the desired value. This leads to substantial reduction of settling time. Also, thanks to self-triggering control, the hardware overhead from counting the event interval is removed without the first response time degradation, achieving high current density. The last design with a 100pF of output capacitor improves settling time and current density by 3.8x and 6.7x, respectively, while achieving comparable transient performance in terms of Figure-of-Merit.
This item is currently under embargo. It will be available starting 2020-05-29.
More About This Work
- Academic Units
- Electrical Engineering
- Thesis Advisors
- Seok, Mingoo
- Ph.D., Columbia University
- Published Here
- July 30, 2019