2025 Theses Doctoral

Novel Vertical-Channel Thin-Film Transistors for Advanced Display Applications

Huang, Zicong

Displays are the primary conduit between digital information and human perception. As emerging OLED and micro-LED pixels demand higher current density, finer resolution, and improved power efficiency, conventional thin-film-transistor (TFT) backplanes face a steep trade-off between performance and manufacturing cost. Shortening the channel length boosts drive current but normally requires sub-micron photolithography that is prohibitively expensive for large-area panels. This dissertation develops two vertical-channel TFT architectures that set the channel length in the film-thickness direction, enabling sub-micron channels using standard large-area processes.

The first architecture—an organic permeable-base transistor (OPBT) defined by a block-copolymer (BCP) template—demonstrates the feasibility of bottom-up channel definition. A complete process was implemented, and devices were measured. Representative transfer characteristics show on–off ratios of ∼ 229 (Device 1) and ∼ 29 (Device 2), with base current ≲ 1 × 10⁻¹⁰ A. However, overall device yield was low, and the output characteristics did not saturate robustly, consistent with challenges in BCP ordering, pattern transfer into thin Al, and the reliability of the oxidized-Al gate dielectric.

Building on these lessons, Chapters 3–5 introduce a bottom-gate/top-contact step-edge IGZO vertical TFT (BG–SEVT). On the first successful test chip (single-channel geometry), 16 of 18 devices were functional (∼ 89% yield). Devices exhibited on/off > 10⁵, low gate leakage, and (at 𝑉_DS = 0.1 V) on-current of about 0.25 μA μm⁻¹. Across the population, the typical subthreshold swing was 1 V/dec⁻¹ to 2 V/dec⁻¹ with a threshold near 0 V to 0.6 V (extracted at 𝑉_DS = 1.0 V). An improved process (Chapter 5) adds a tapered low-temperature PECVD SiO₂ spacer that strengthens the gate–top overlap and enables an ALD HfO₂ gate dielectric. After an 225 ◦C, 30 min air anneal, the subthreshold swing was reduced to as low as ∼ 114 mV/dec⁻¹ (thin-stack case) and ∼ 257 mV/dec⁻¹ (thicker-stack case); measured datasets at 𝑉_DS = 2.0 V show on/off > 10₂ with |𝑰_𝐷| > 1 μA μm⁻¹ across the tested devices, with champion devices reaching on/off > 10⁷ and |𝑰_𝐷| > 10 μA/μm. Post-anneal functional yield in a larger population was ∼ 87% (7/8) for single-channel devices and ∼ 79% (19/24) for dual-channel ones. A trade-off was observed: annealing improved turn-off characteristics and threshold stability but reduced on-current and apparent field-effect mobility.

Collectively, the thesis documents the from-scratch development of two lithography-light vertical TFT platforms, quantifies their performance/yield limits and process windows, and outlines practical routes to improve electrostatic control, contact/series resistance, and stability. While further optimization is required for industrial deployment, these architectures expand the design space for cost-effective, high-resolution display backplanes and other large-area electronic systems.