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An Eight-Processor Chip for a Massively Parallel Machine

Shaw, David Elliot; Sabety, Theodore M.

This paper describes a VLSI chip that serves as the basis for a massively parallel tree machine called: NON-VON 3. The chip, which is implemented in 3-micron nMOS technology, contains eight 8-bit processing elements (PE's), each embodying 64 bytes of static RAM. Significant features of the design Include: an unusually high processor density, a novel I/O switch that allows the machine to dynamically reconfigure to realize several logical communication topologies; logic supporting the pipelining of instructions, both within and among the individual PE's; a shared partial Instruction decoder that reduces pinout and area, and a parallel self-testing, dynamically reconfigurable, fault-tolerant RAM that significantly increases both yield and reliability. The design and operation of the chip are discussed, along with its speed, area, and power dissipation characteristics.



More About This Work

Academic Units
Computer Science
Department of Computer Science, Columbia University
Columbia University Computer Science Technical Reports, CUCS-133-84
Published Here
February 22, 2012