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Reconciling Repeatable Timing with Pipelining and Memory Hierarchy

Edwards, Stephen A.; Kim, Sungjun; Lee, Edward A.; Patel, Hiren D.; Schoeberl, Martin

This paper argues that repeatable timing is more important and more achievable than predictable timing. It describes microarchitecture approaches to pipelining and memory hierarchy that deliver repeatable timing and promise comparable or better performance compared to established techniques. Specifically, threads are interleaved in a pipeline to eliminate pipeline hazards, and a hierarchical memory architecture is outlined that hides memory latencies.

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Computer Science
Published Here
August 23, 2011

Notes

Workshop on Reconciling Performance with Predictability, October 15, 2009.

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