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A Disruptive Computer Design Idea: Architectures with Repeatable Timing

Edwards, Stephen A.; Kim, Sungjun; Lee, Edward A.; Liu, Isaac; Patel, Hiren D.; Schoeberl, Martin

This paper argues that repeatable timing is more important and more achievable than predictable timing. It describes microarchitecture approaches to pipelining and memory hierarchy that deliver repeatable timing and promise comparable or better performance compared to established techniques. Specifically, threads are interleaved in a pipeline to eliminate pipeline hazards, and a hierarchical memory architecture is outlined that hides memory latencies.



Also Published In

2009 IEEE International Conference on Computer Design

More About This Work

Academic Units
Computer Science
IEEE Service Center
Published Here
August 23, 2011
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