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Predictable Programming on a Precision Timed Architecture

Lickly, Ben; Liu, Isaac; Kim, Sungjun; Patel, Hiren D.; Edwards, Stephen A.; Lee, Edward A.

In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies, but without precise worst-case execution time bounds they cannot provide guarantees. We describe an alternative in this paper: a SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control. Its pipeline executes multiple, independent hardware threads to avoid costly, unpredictable bypassing, and its exposed memory hierarchy provides predictable latency. We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.

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Title
Proceedings of the 2008 International Conference on Compilers, Architectures and Synthesis for Embedded Systems: October 19-24, 2008, Atlanta, GA, USA
Publisher
ACM Press
DOI
https://doi.org/10.1145/1450095.1450117

More About This Work

Academic Units
Computer Science
Published Here
September 20, 2011