An Implementation of a Renesas H8/300 Microprocessor with a Cycle-Level Timing Extension

Huang, Chen-Chun; Coca, Javier; Gupta, Yashket; Edwards, Stephen A.

We describe an implementation of the Renesas H8/300 16-bit processor in VHDL suitable for synthesis on an FPGA. We extended the ISA slightly to accomodate cycle-accurate timers accessible from the instruction set, designed to provide more precise real-time control. We describe the architecture of our implementation in detail, describe our testing strategy, and finally show how to built a cross compilation toolchain under Linux.



More About This Work

Academic Units
Computer Science
Department of Computer Science, Columbia University
Columbia University Computer Science Technical Reports, CUCS-051-06
Published Here
April 28, 2011