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Theses Doctoral

Design and Optimization of Low-power Level-crossing ADCs

Weltin-Wu, Colin

This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit.

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More About This Work

Academic Units
Electrical Engineering
Thesis Advisors
Tsividis, Yannis P.
Degree
Ph.D., Columbia University
Published Here
March 20, 2014