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Synthesis of High-Performance Packet Processing Pipelines

Soviani, Cristian; Hadzic, Ilija; Edwards, Stephen A.

Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the features of the system. We propose a high-level synthesis technique for a new model for representing packet editing functions. Experiments show our circuits achieve a throughput of up to 40Gb/s on a commercially available FPGA device, equal to state-of-the-art implementations.

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Title
Proceedings 2006: Design Automation Conference, the Moscone Center, San Francisco, CA, July 24-28, 2006
Publisher
IEEE
DOI
https://doi.org/10.1109/DAC.2006.229316

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Academic Units
Computer Science
Published Here
September 22, 2011