2017 Articles
From Functional Programs to Pipelined Dataflow Circuits
We present a translation from programs expressed in a functional IR into dataflow networks as an intermediate step within a Haskell-to-Hardware compiler. Our networks exploit pipeline parallelism, particularly across multiple tail-recursive calls, via non-strict function evaluation. To handle the long-latency memory operations common to our target applications, we employ a latency-insensitive methodology that ensures arbitrary delays do not change the functionality of the circuit. We present empirical results comparing our networks against their strict counterparts, showing that nonstrictness can mitigate small increases in memory latency and improve overall performance by up to 2x.
Files
- p76-townsend.pdf application/pdf 254 KB Download File
Also Published In
- Title
- Proceedings of the 26th International Conference on Compiler Construction
- Publisher
- Association for Computing Machinery
- DOI
- https://doi.org/10.1145/3033019.3033027
More About This Work
- Academic Units
- Computer Science
- Publisher
- Association for Computing Machinery
- Published Here
- June 5, 2017