2026 Theses Doctoral

Architecture and Circuit Design for Machine Learning with In-Memory Computing

Lin, Chuan-Tung

The expansion of the Internet of Things (IoT) ecosystem has fueled the need for intelligent, low-power, and resource-efficient machine learning solutions that can operate directly on edge devices. Tiny Machine Learning (TinyML) has emerged as a promising paradigm to address this need by enabling deep neural network (DNN) inference on highly constrained platforms such as microcontrollers and wearable devices. While DNNs have achieved state-of-the-art performance in applications like face recognition, object detection, and speech recognition, deploying them locally on edge devices presents significant challenges due to stringent limitations in computation, memory, and energy. Executing inference on-device, rather than offloading it to cloud servers, helps reduce data transfer latency, improve reliability, and enhance user privacy. Consequently, minimizing power consumption and maximizing energy efficiency are critical goals in TinyML design, as they directly influence battery life, charging frequency, and overall system sustainability.

Low-power AI hardware plays a pivotal role in realizing the vision of TinyML, enabling continuous and autonomous intelligence in power-constrained environments. Such hardware can support always-on functions, including keyword spotting, visual wake-up, and gesture recognition, to trigger higher-level processing only when necessary. It also extends to applications in security monitoring, battery-powered cameras, and micro aerial vehicles, where real-time inference must occur under tight energy budgets. To achieve this, researchers have explored power reduction techniques across multiple abstraction levels—spanning algorithms, architectures, and circuits. Application-driven, full-stack co-optimization that jointly considers task characteristics and hardware constraints has proven particularly effective in minimizing energy consumption while maintaining the required performance and accuracy.

This thesis presents my research on architecture and circuit design with in-memory computing for machine learning and AI applications. Chapters 2 to 5 list my past works. The first work describes a digital in-memory computing hardware that utilizes approximate arithmetic hardware for improved area and energy efficiency. The second work presents a floating-point in-memory computing hardware with approximate logics to improve the energy efficiency, throughput, and weight density. The third and fourth works demonstrate in-memory computing-based microcontroller units with on-chip training using hardware, software, and dataflow optimizations.