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Design Techniques for Frequency Synthesizers in Highly Scaled CMOS Technologies

Shih-An Yu

Title:
Design Techniques for Frequency Synthesizers in Highly Scaled CMOS Technologies
Author(s):
Yu, Shih-An
Thesis Advisor(s):
Kinget, Peter R.
Date:
Type:
Dissertations
Department:
Electrical Engineering
Permanent URL:
Notes:
Ph.D., Columbia University.
Abstract:
While extremely scaled CMOS transistors are believed to cause many design concerns especially for conventional analog circuits, CMOS technology scaling, on the other hand, has also opened up new opportunities for analog and mixed-mode circuit designs to mitigate design challenges by the speed improvement and the high density of the nanometer devices. Phase-locked-loop-based frequency synthesizers are essential building blocks in almost all the communication systems. The design of PLLs is a true mixed signal design challenge covering from high speed analog and RF blocks (VCO), to high speed digital blocks (dividers), to low speed analog (charge pump and loop filter) and low speed digital (phase frequency detector) circuits. In this thesis, we study design challenges and present corresponding solutions to realize PLLs in the nano-scale CMOS era. In particular we focus on supply voltage scaling, area scaling, ultra-wide frequency range, and ultra-low noise performance. An ultra low voltage (ULV) 2.5-GHz GFSK modulator implemented in a 90-nm CMOS technology using only standard digital regular Vt (RVT) devices will first be introduced to address robustness concerns and speed issues due to the supply voltage scaling (down to 0.5V). Then, a 2.5-GHz ultra-compact (150um x 280um) analog PLL implemented in a 45-nm CMOS technology with a fully integrated LC-VCO and an on-chip passive R-C loop filter will further be used to show that area scaling can indeed be achieved for a PLL through a rigorous area-scaling scheme of LC oscillators and a new loop filter structure. New emerging applications such as software-defined radios or highly integrated test instrumentation require the PLL synthesizer to have ultra wide bandwidth and ultra low phase noise. We will present the approaches to mitigate these challenging design objectives by exploiting the capabilities of nanometer transistors. A wideband synthesizer covering from 125MHz to 32GHz with a constant performance across the entire frequency range will be presented; the scaling schemes and design methodologies to achieve constant noise performance across the ultra-wide frequency range will be discussed. Finally, an ultra low noise fractional-N synthesizer will be presented to show how low phase noise fractional-N frequency synthesis can be achieved by taking the full advantage of nano-scale CMOS transistors.
Subject(s):
Electrical engineering
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