Clocking Schemes for High Speed Digital Systems

Stephen Unger; Chung-Jen Tan

Clocking Schemes for High Speed Digital Systems
Unger, Stephen
Tan, Chung-Jen
Technical reports
Computer Science
Permanent URL:
Columbia University Computer Science Technical Reports
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Department of Computer Science, Columbia University
Publisher Location:
New York
A key element (one is tempted to say the heart) of most digital systems is the clock. Its period determines the rate at which data are processed, and so should be made as small as possible, consistent with reliable operation. Based on a worst case analysis, clocking schemes for high-performance systems are analyzed. These are 1- and 2-phase systems using simple clocked latches, and 1-phase systems using edge-triggered D-flip-flops. Within these categories (any of which may be preferable in a given situation), it is shown how optimal tradeoffs can be made by appropriately choosing the parameters of the clocking system as a function of the technology parameters. The tradeoffs involve the clock period (which of course determines the data rate) and the tolerances that must be enforced on the propagation delays through the logic. Clock-pulse edge tolerances are shown to be an important factor. It is shown that, for systems using latches, their detrimental effects on the clock period can be converted to tighter bounds on the short-path delays by allowing D changes to lag behind the leading edges of the clock pulses and by using wider clock pulses or, in the case of 2-phase systems, by overlapping the clock pulses.
Computer science
Artificial intelligence
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