Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks
- Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks
- Kim, Martha Allen
Edwards, Stephen A.
- Computer Science
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- AMAS-BT - 3rd Workshop on Architectural and Microarchitectural Support for Binary Translation
- The world needs special-purpose accelerators to meet future constraints on computation and power consumption. Choosing appropriate accelerator architectures is a key challenge. In this work, we present a pintool designed to help evaluate the potential benefit of accelerating a particular function. Our tool gathers cross-procedural data usage patterns, including implicit dependencies not captured by arguments and return values. We then use this data to characterize the limits of hardware procedural acceleration imposed by on-chip communication and storage systems. Through an understanding the bottlenecks in future accelerator-based systems we will focus future research on the most performance-critical regions of the design. Accelerator designers will also find our tool useful for selecting which regions of their application to accelerate.
- Computer science
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- Suggested Citation:
- Martha Allen Kim, Stephen A. Edwards, 2010, Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks, Columbia University Academic Commons, https://doi.org/10.7916/D8K64TFN.