Analog Circuit Design Techniques At 0.5 V

This thesis presents design techniques that make possible the operation of analog circuits with ultra-low supply voltages, down to 0.5 V. The work is motivated by the need to be able to design circuits for nano-scale devices. The techniques presented in this thesis are true low voltage techniques---all nodes in the circuits are within the power supply rails of 0 and 0.5 V.

We use the design of OTAs as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. The OTAs include common-mode feedback and feed-forward circuits to allow maximum common-mode rejection. Au tomatic biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage and temperature are discussed. Prototype chips were fabricated in a 0.18 mum CMOS process using standard 0.5 V VT devices. The body-input OTA has a measured 52 dB DC gain, a 2.5 MHz gain-bandwidth and consumes 110 muW. The gate-input OTA has a measured 62 dB DC gain (with automatic gain-enhancement), a 10 MHz gain-bandwidth and consumes 75 muW.

A weak-inversion MOS variable capacitor is proposed and modeled. The variable capacitors are used along with 0.5 V gate-input OTAs to implement a fully integrated, tunable, active-RC, 135 kHz 5th-order elliptic low-pass filter. The prototype chip in a 0.18 mum CMOS process with V T of 0.5 V also includes an on-chip PLL for tuning. The 1 mm 2 chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5 V supply.

A track-and-hold (T/H) circuit is a fundamental building block for discrete-time signal processing applications. The design of a 0.5 V TIH circuit is discussed. A 0.5 V gate-input OTA with its associated bias circuitry is used to implement the TIH circuit on a 0.25 mum CMOS process. The design achieves 60 dB of SNDR at a 1 MSample/sec sampling rate, with a power consumption of 1 mW from the 0.5 V supply.